1. Field of the Invention
The present invention relates generally to methods of fabricating semiconductor devices and particularly to methods of fabricating semiconductor devices with a capacitor.
To store information, semiconductor devices are used. One such device is dynamic random access memory (DRAM). To allow a DRAM to steadily store an electric charge serving as information as a design rule is reduced, a variety of approaches has been proposed to ensure that its capacitor has sufficient capacity.
2. Description of the Background Art
To ensure that a capacitor has sufficient capacity, Japanese Patent Laying-Open No. 2001-203334 proposes to provide a surface of an electrode (a storage node) of a capacitor with protrusions and depressions to allow the storage node and a capacitor insulation film to contact each other over an increased area.
The publication describes a method of fabricating a semiconductor device, as will be described hereinafter. Initially, a memory cell transistor or the like formed on a semiconductor substrate is covered with an interlayer insulation film for example of silicon oxide film. The interlayer insulation film is provided with a contact hole exposing the memory cell transistor.
Subsequently a doped polysilicon film is deposited on the interlayer insulation film to fill the contact hole. The doped polysilicon film has a surface entirely etched back to remove the doped polysilicon film from an upper surface of the interlayer insulation film while allowing the doped polysilicon film to remain in the contact hole. A bottom electrode plug is thus provided in the contact hole.
Subsequently a silicon nitride film is deposited on the interlayer insulation film as an etching stopper to cover the bottom electrode plug. On the silicon nitride film a silicon oxide film is deposited for providing a storage node.
Subsequently a prescribed resist pattern is formed on the silicon oxide film. The resist pattern is used as a mask to etch the silicon oxide film to form an opening exposing a surface of the bottom electrode plug.
Subsequently a doped polysilicon film and an amorphous silicon film are deposited on the silicon oxide film including the interior of the opening. Then the amorphous silicon film is roughened as prescribed to provide a rugged grain polysilicon (RGP) film.
Subsequently an insulation film is deposited on the RGP film to fill the opening. The insulation film is chemically mechanically polished to remove the RGP film and the doped polysilicon film from the silicon oxide film while the RGP film remains in the opening. Electrical isolation from an adjacent storage node is thus achieved.
Subsequently the insulation film on the RGP film is removed and furthermore the silicon oxide film surrounding the RGP film is removed. A storage node by the RGP film is thus exposed.
Subsequently a capacitor insulation film is deposited to cover the RGP film. On the capacitor insulation film a titanium nitride (TiN) film and a polysilicon film are deposited to serve as a cell plate. A capacitor including the storage node, the capacitor insulation film and the cell plate is thus provided.
Thereafter another interlayer insulation film is deposited to cover the capacitor and furthermore on the interlayer insulation film a prescribed interconnect layer is deposited to complete a main portion of the DRAM.
The above described, conventional method of fabricating a DRAM, however, has the following disadvantage: in the conventional method in forming the storage node the storage node is isolated after a roughening step is performed to prevent short circuit between adjacent storage nodes. In other words, the insulation film introduced into the opening is CMPed after the amorphous silicon film is roughened as prescribed.
After the amorphous silicon film is roughened and before the capacitor insulation film is deposited, a semiconductor substrate is CMPed, etched, and the like, and such steps may disadvantageously remove the RGP film. Consequently, the capacitor may have insufficient capacity.